Friday, 5 April 2013

We have some RAMs

The next "milestone" for the 6809-on-a-breadboard computer project is to gain some RAM.  Computers can't do very much unless they can store things.

This was fairly easy, though I did have to fix one problem with the current circuit.  I need to do some more research on this subject to understand the issue fully, but briefly...

Previously, in the EEPROM only test, I was feeding the E (Enable) output from the 6809 through to the Enable pin on the address decoder, which was then used to form the Chip Select for the EEPROM. Meanwhile the /OE and R/W line for the EEPROM came more or less directly from the R/W line on the 6809.  This works ok (but wrong) when only the EEPROM is in play, but is not sufficient or correct when RAM is added.

The adjusted circuit instead uses a tied low (always active) E pin on the decoder, and instad combines the E and R/W pins on the 6809 to form the R/W and /OE on the EEPROM (and RAM).  This is shown in the bottom left of the diagram.

The decoder's remaining two outputs are ORd (inverse logic means an AND gate, formed from a NAND and a NOT) together to form the /CS of the RAM, meaning the lower 32KByte of the 64KByte total address space is Chip Selected into the RAM chip.  I found an Aliance AS6C4008 (PDF) static RAM on eBay for a few pounds; it is a 512KByte, 32pin PDIP IC.  Obviously 512KByte requires more address lines then the 6809 has (19 vs 16).  In time I might devise a bank switching circuit to make use of this "massive" memory, but for now my circuit uses only 15 lines, yielding 32Kbyte, and ties the other four low.

The RAM is at the right.

To exercise the RAM, and prove that it is working correctly, I have made some changes to my test program:
  • It now makes use of a couple of simple subroutines (which involves the use of a stack in RAM)
  • The pattern of LEDs to show is copied from EEPROM to RAM at startup, and then shown from RAM
  • The pattern is modified (inverted) after it is shown, so the next pass through the loop will show a reversed pattern
  • The delay (speed) that the pattern is shown is held in a memory location and adjusted on each run through
The updated program (ramtest.a) is on github, as usual.

And here is a picture of the breadboard:

It's getting crowded in there!  Right of the MPU (middle row) is the 4 in 2 address decoder, NOT gates (74HC04) and NAND gates (74HC00).  The RAM is at the bottom middle.  Left of it is the unwired MC6850 UART, which will be my next addition.  That IC is the oldest on the board, dated the 18th week of 1982.  It shall be interesting to see if it still works (I would be amazed if it did not).

Today at work I received the PCB for the EEPROM programmer.  Total time to have the board made up in China and receive the board - less then 2 weeks.  Pretty impressive stuff.  Total cost, of 10 identical 10cm by 10cm boards, was about 37 pounds.  Hopefully I will get a chance to solder up the board over the weekend.  Whilst I'm happy with my stripboard programmer, the PCB version certainly looks a lot nicer.

Thanks again to Richard Gellman for turning my circuit into a PCB design!

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